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? semiconductor components industries, llc, 2017 january, 2017 ? rev. 6 1 publication order number: ncp81245/d ncp81245 three-rail output controller with single intel proprietary interface for desktop and notebook cpu applications the ncp81245 (3+3+1 phase) three?output buck solution is optimized for intel?s imvp8 cpus. the two multi?phase rail control systems are based on dual?edge pulse?width modulation (pwm) combined with dcr current sensing providing an ultra fast initial response to dynamic load events and reduced system cost. the single?phase rail makes use of on semiconductor?s patented high performance rpm operation. rpm control maximizes transient response while allowing for smooth transitions between discontinuous?frequency?scaling operation and continuous?mode full?power operation. the ncp81245 has an ultra?low offset current monitor amplifier with programmable offset compensation for high?accuracy current monitoring. three?phase rails feature ? dual edge modulation for fastest initial response to transient loading ? high performance operational error amplifier ? digital soft start ramp ? dynamic reference injection ? accurate total summing current amplifier ? dual high impedance differential voltage and total current sense amplifiers ? phase?to?phase dynamic current balancing ? true differential current balancing sense amplifiers for each phase ? adaptive voltage positioning (avp) ? switching frequency range of 300 khz ? 750 khz ? vin range 4.5 v to 20 v ? startup into pre?charged loads while avoiding false ovp ? ultrasonic operation ? these devices are pb?free and are rohs compliant single?phase rail features ? enhanced rpm control system ? ultra low offset iout monitor ? dynamic vid feed?forward ? programmable droop gain ? zero droop capable ? thermal monitor ? ultrasonic operation ? adjustable vboot ? digitally controlled operating frequency applications ? desktop & notebook processors ? gaming marking diagram www. onsemi.com 52 1 qfn52 mn suffix case 485be f = wafer fab a = assembly site wl = lot id yy = year ww = work week = pb?free package ncp81245 fawlyyww device package shipping ? ordering information ncp81245mntxg qfn52 (pb?free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d.
ncp81245 www. onsemi.com 2 ncp81245 ntc pwm1 dron pwm2 pwm3 cscomp ilim cssum csp1 csp2 csp3 csref vsp vsn diffout fb comp +5v vcc iout ntc tsense vrhot vpu gnd skt_sns+ skt_sns? sdio alert sclk vpu vpu ntc tsense batt chrgr psys iout skt_sns+ skt_sns? vsp vsn diffout fb comp vrrdy en ntc pwm csp csn ilim skt_sns+ skt_sns? vsp vsn comp vrmp vin iout vcc_rail1 vcc_rail3 hg sw lg bst pwm en vcc vdrv vin pgnd smod zcd gnd vin on drmos hg sw lg bst pwm en vcc vdrv vin pgnd smod zcd gnd vin on drmos hg sw lg bst pwm en vcc vdrv vin pgnd smod zcd gnd vin on drmos hg sw lg bst pwm en vcc vdrv vin pgnd smod zcd gnd vin on drmos ntc pwm1 dron pwm2 pwm3 cscomp ilim cssum csp1 csp2 csp3 csref vcc_rail2 hg sw lg bst pwm en vcc vdrv vin pgnd smod zcd gnd vin on drmos hg sw lg bst pwm en vcc vdrv vin pgnd smod zcd gnd vin on drmos hg sw lg bst pwm en vcc vdrv vin pgnd smod zcd gnd vin on drmos figure 1.
ncp81245 www. onsemi.com 3 vsp_3ph_a vsn_3ph_a 1 2 3 4 5 6 7 8 imon_3ph_a diffout_3ph_a fb_3ph_a comp_3ph_a ilim_3ph_a cscomp_3ph_a cssum_3ph_a 10 11 12 13 csref_3ph_a csp1_3ph_a csp2_3ph_a csp3_3ph_a vrhot# vsp_3ph_b 39 38 37 36 35 34 33 32 vsn_3ph_b imon_3ph_b diffout_3ph_b fb_3ph_b comp_3ph_b ilim_3ph_b cscomp_3ph_b 31 30 29 28 27 cssum_3ph_b csref_3ph_b csp1_3ph_b csp2_3ph_b ncp81245 tab: ground figure 2. pinout 9
ncp81245 www. onsemi.com 4 programming detection monitor amp dac ovp comparators max overcurrent overcurrent current current comparators uvlo & en error interface svid mux monitor thermal psys 46 iccmax_2ph 18 vrhot# 31 sdio 32 alert# 33 sclk 34 iccmax_1a 19 rosc_saus 15 r osc_coregt 14 vrmp 12 iccmax_1b 20 vsp_2ph 47 _ + sense balance current amplifiers amp & logic state power pwm adc generators dac oscillator & ramp generators logic vr ready data registers iph2 current dac ovp iph1 ocp forward 1.3v enable gate amp comp vsn vsp ps# pwm1_2ph 16 pwm2_2ph 17 iout_2ph pwm2 1.3v _ _ + vr_rdy 38 vsn vsp pwm1 buffer diffout_2 ph 2 csp2_2ph 9 csp1_2ph 10 drvon 35 csref_2ph 8 cssum_2ph 7 cscomp_2 ph 6 ilim_2ph 5 iout_2ph 1 fb_2ph 3 vsn_2ph 48 comp_2ph 4 enable ps# drvon ps# ps# vrmp cscomp csref addr_vboot 21 iout feed? zero ovp enable enable ovp ocp ovp drvon ocp ovp diff tsense_2ph 11 tsense_1ph 23 iout_1a iout_1b vcc 13 en 37 ground 49 figure 3. block diagram of dual edge architecture
ncp81245 www. onsemi.com 5 vsp_1a 24 pwm_1a 22 comp_1a 26 csp_1a 29 csn_1a 28 ilim_1a 27 iout_1a 30 vsn_1a 25 programming detection monitor comparators ovp ref overcurrent overcurrent current current sense amp pwm generator dac ramp generator current dac ocp forward ps# vsn vsp dac dac vrmp iout feed? zero ovp curr dac feedforward current droop current ocp ref pwm ramp freq from svid interface ocp _ + av=1 gm gm gm gm comp ovp drvon figure 4. block diagram of enhanced rpm architecture
ncp81245 www. onsemi.com 6 table 1. qfn52 pin list description pin name description 1 vsp_3ph_a differential output voltage sense positive for multi?phase rail ?a? 2 vsn_3ph_a differential output voltage sense negative for multi?phase rail ?a? 3 imon_3ph_a a resistor to ground programs iout gain for multi?phase rail ?a? 4 diffout_3ph_a output of multi?phase rail ?a? differential remote sense amplifier 5 fb_3ph_a error amplifier voltage feedback for multi?phase rail ?a? 6 comp_3ph_a error amplifier output and pwm comparator inverting input for multi?phase rail ?a? 7 ilim_3ph_a a resistor to cscomp_3ph_a programs the over?current threshold for multi?phase rail ?a? 8 cscomp_3ph_a total?current?sense amplifier output for multi?phase rail ?a? 9 cssum_3ph_a inverting input of total?current?sense amplifier for multi?phase rail ?a? 10 csref_3ph_a total?current?sense amplifier reference voltage input for multi?phase rail ?a? 11 csp1_3ph_a current?balance amplifier positive input for phase 1 of multi?phase rail ?a? 12 csp2_3ph_a current?balance amplifier positive input for phase 2 of multi?phase rail ?a? 13 csp3_3ph_a current?balance amplifier positive input for phase 3 of multi?phase rail ?a? 14 ttsense_3ph_a temperature sense input for multi?phase rail ?a? 15 vrmp vin feed?forward input. controls a current used to generate the ramps of the modulators 16 vcc power for the internal control circuits. a decoupling capacitor is connected from this pin to ground 17 dron external fet driver enable for discrete driver or drmos 18 pwm1_3ph_a / iccmax_3ph_a phase 1 pwm output of multi?phase rail ?a? / a resistor to ground programs iccmax for multi?phase rail ?a? 19 pwm2_3ph_a / addr phase 2 pwm output of multi?phase rail ?a? / a resistor to ground configures intel proprietary interface addresses for all 3 rails (addr) 20 pwm3_3ph_a / vboot phase 3 pwm output of multi?phase rail ?a? / a resistor to ground configures boot voltage for all 3 rails (vboot) 21 pwm3_3ph_b / rosc_3ph phase 3 pwm output of multi?phase rail ?b? / phase 4 pwm output of multi?phase rail ?a? / a resistor to ground configures fsw for both ?a? and ?b? multi?phase rails (rosc_3ph) 22 pwm2_3ph_b / rosc_1ph phase 2 pwm output of multi?phase rail ?b? / a resistor to ground configures fsw for 1ph rail (rosc_1ph) 23 pwm1_3ph_b / iccmax_3ph_b phase 1 pwm output of multi?phase rail ?b? / a resistor to ground programs iccmax for multi?phase rail ?b? 24 ttsense_1ph / psys temperature sense input for the single?phase rail / system input power monitor. a resistor to ground scales this signal 25 ttsense_3ph_b temperature sense input for multi?phase rail ?b? 26 csp3_3ph_b current?balance amplifier positive input for phase 3 of multi?phase rail ?b? / phase 4 of multi?phase rail ?a? 27 csp2_3ph_b current?balance amplifier positive input for phase 2 of multi?phase rail ?b? 28 csp1_3ph_b current?balance amplifier positive input for phase 1 of multi?phase rail ?b? 29 csref_3ph_b total?current?sense amplifier reference voltage input for multi?phase rail ?b? 30 cssum_3ph_b inverting input of total?current?sense amplifier for multi?phase rail ?b? 31 cscomp_3ph_b total?current?sense amplifier output for multi?phase rail ?b? 32 ilim_3ph_b a resistor to cscomp_3ph_b programs the over?current threshold for multi?phase rail ?b? 33 comp_3ph_b error amplifier output and pwm comparator inverting input for multi?phase rail ?b? 34 fb_3ph_b error amplifier voltage feedback for multi?phase rail ?b? 35 diffout_3ph_b output of multi?phase rail ?b? differential remote sense amplifier 36 imon_3ph_b a resistor to ground programs iout gain for multi?phase rail ?b? 37 vsn_3ph_b differential output voltage sense negative for multi?phase rail ?b?
ncp81245 www. onsemi.com 7 table 1. qfn52 pin list description pin description name 38 vsp_3ph_b differential output voltage sense positive for multi?phase rail ?b? 39 vr_hot# thermal logic output for over?temperature condition on ttsense pins 40 sdio serial vid data interface 41 alert# serial vid alert# 42 sclk serial vid clock 43 en enable input. high enables all three rails 44 pwm_1ph / iccmax_1ph pwm output of the single?phase rail / a resistor to ground programs iccmax for the single?phase rail 45 vr_rdy vr_rdy indicates all three rails are ready to accept intel proprietary interface commands 46 imon_1ph a resistor to ground programs iout gain for the single?phase rail 47 csp_1ph differential current sense positive for the single?phase rail 48 csn_1ph differential current sense negative for the single?phase rail 49 ilim_1ph a resistor to ground programs ilim gain for the single?phase rail 50 comp_1ph compensation for single?phase rail 51 vsn_1ph differential output voltage sense negative for single?phase rail 52 vsp_1ph differential output voltage sense positive for single?phase rail 53 ta b gnd electrical information table 2. absolute maximum ratings pin symbol v max v min i source i sink compx vcc + 0.3 v ?0.3 v 2 ma 2 ma cscompx vcc + 0.3 v ?0.3 v 2 ma 2 ma vsn gnd + 300 mv gnd?300 mv 1 ma 1 ma vrdy vcc + 0.3 v ?0.3 v n/a 2 ma vcc 6.5 v ?0.3 v n/a n/a vrmp +25 v ?0.3 v all other pins vcc + 0.3 v ?0.3 v stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. *all signals referenced to gnd unless noted otherwise. table 3. thermal information description symbol typ unit thermal characteristic qfn package (note 1) r ja 68 c/w operating junction temperature range (note 2) t j ?40 to +125 c operating ambient temperature range ?40 to +100 c maximum storage temperature range t stg ?40 to +150 c moisture sensitivity level qfn package msl 1 *the maximum package power dissipation must be observed. 1. 2) jesd 51?5 (1s2p direct?attach method) with 0 lfm 2. 3) jesd 51?7 (1s2p direct?attach method) with 0 lfm
ncp81245 www. onsemi.com 8 table 4. electrical characteristics unless otherwise stated: ?40 c < t a < 100 c; 4.75 v < v cc < 5.25 v ; c vcc = 0.1 f parameter test conditions min typ max unit error amplifier input bias current ?900 900 na open loop dc gain cl = 20 pf to gnd, rl = 10 k to gnd 80 db open loop unity gain bandwidth cl = 20 pf to gnd, rl = 10 k to gnd 20 mhz slew rate vin = 100 mv, g = ?10 v/v, vout = 0.75 v ? 1.52 v, cl = 20 pf to gnd, dc load = 10k to gnd 5 v/ s maximum output voltage i source = 2.0 ma 3.5 v minimum output voltage i sink = 2.0 ma 1 v differential summing amplifier input bias current ?25 25 na vsp input voltage range ?0.3 3.0 v vsn input voltage range ?0.3 0.3 v ?3db bandwidth cl = 20 pf to gnd, rl = 10 k to gnd 22.5 mhz closed loop dc gain vs to diff vs+ to vs? = 0.5 to 1.3 v 1.0 v/v maximum output voltage i source = 2 ma 3.5 v minimum output voltage i sink = 2 ma 0.8 v current summing amplifier offset voltage (vos) ?300 300 v input bias current csref= 1 v ?7.5 7.5 a input bias current cssum= 1 v ?7.5 7.5 na open loop gain 80 db current sense unity gain bandwidth c l = 20 pf to gnd, r l = 10 k to gnd 15 mhz maximum cscomp (a) output voltage isource = 2 ma 3.5 v minimum cscomp(a) output voltage isink = 500 ua 0.15 v current balance amplifier input bias current cspx ? cspx + 1 = 1.2 v ?50 50 na common mode input voltage range cspx = csref 0 2.3 v differential mode input voltage range csnx = 1.2 v ?100 100 mv closed loop input offset voltage matching cspx = 1.2 v, measured from the average ?1.5 1.5 mv current sense amplifier gain 0v < cspx < 0.1 v, 5.7 6.0 6.3 v/v multiphase current sense gain matching csref = csp = 10 mv to 30 mv ?3 3 % ?3db bandwidth 8 mhz bias supply supply voltage range 4.75 5.25 v vcc quiescent current enable high 33 50 ma vcc quiescent current enable low 60 a
ncp81245 www. onsemi.com 9 table 4. electrical characteristics unless otherwise stated: ?40 c < t a < 100 c; 4.75 v < v cc < 5.25 v ; c vcc = 0.1 f parameter unit max typ min test conditions bias supply uvlo threshold vcc rising 4.5 v vcc falling 4 vcc uvlo hysteresis 250 mv vrmp supply range 4.5 20 v uvlo threshold vramp rising 4.25 v vramp falling 3 v uvlo hysteresis 675 mv dac slew rate slew rate fast >10 mv/ s soft start slew rate 1/2 sr fast mv/ s slew rate slow 1/2 sr fast mv/ s enable input enable high input leakage current enable = 0 ?1 1 a v ih 0.8 v v il 0.3 v enable delay time measure time from enable tran- sitioning hi , vboot is not 0 v 2.5 ms dron output high voltage sourcing 500 a 3.0 v output low voltage sinking 500 a 0.1 v pull up resistances 2.0 k rise/fall time cl (pcb) = 20 pf, vo = 10% to 90% 160 ns internal pull down resistance v cc = 0 v 70 k overcurrent protection ilim threshold current (delayed ocp shutdown) ps0 9 10 11 a ps1, ps2, ps3 (n = ps0 phase count) 10/n ilim threshold current (immediate ocp shutdown) ps0 13.5 15 16.5 a ps1, ps2, ps3 (n = ps0 phase count) 15/n shutdown delay immediate 300 ns delayed 50 s ilim output voltage offset ilim sourcing 10 a ?2 2 mv iout_3ph_a/iout_3ph_b output output offset current v ilim = 5 v 0.25 a output current max ilimit sink current 20 a 200 a current gain (iout current)/(ilimit current) rlim = 20k, riout = 5k dac = 0.8 v, 1.25 v, 1.52 v 9.5 10 10.5 a/a
ncp81245 www. onsemi.com 10 table 4. electrical characteristics unless otherwise stated: ?40 c < t a < 100 c; 4.75 v < v cc < 5.25 v ; c vcc = 0.1 f parameter unit max typ min test conditions oscillator switching frequency range 300 1200 khz switching frequency accuracy 300 khz < fsw < 1 mhz ?10 10 % output over voltage & under voltage protection (ovp & uvp) over voltage threshold during soft?start 1.9 2.0 2.1 v over voltage threshold above dac vsp rising 370 400 430 mv over voltage delay vsp rising to pwmx low 25 ns under voltage threshold below dac?droop vsp falling 225 300 370 mv under?voltage hysteresis vsp rising 25 mv under?voltage delay 5 s modulators (pwm comparators) for a rail & b rail minimum pulse width fsw = 350 khz 40 ns 0% duty cycle comp voltage when the pwm outputs remain lo 1.3 v 100% duty cycle comp voltage when the pwm outputs remain hi vrmp=12.0v 2.5 v pwm phase angle error between adjacent phases 5 tsense vrhot assert threshold 468 mv vrhot rising threshold 488 mv alert assertion threshold 488 mv alert rising threshold 510 mv tsense bias current 115 120 125 a vrhot output low saturation voltage i vr_hot = ?4 ma 0.3 v output leakage current high impedance state ?1 1 a adc voltage range 0 2 v total unadjusted error (tue) ?1 1 % differential nonlinearity (dnl) 8?bit 1 lsb power supply sensitivity +/?1 % conversion time 7.4 s round robin 206 s vrdy output output low saturation voltage i vr_rdy = 4 ma 0.3 v rise time external pull?up of 1 k to 3.3 v c tot = 45 pf, vo = 10% to 90% 150 ns fall time external pull?up of 1 k to 3.3 v c tot = 45 pf, vo = 90% to 10% 150 ns output leakage current when high vr_rdy = 5.0 v ?1 1 a vr_rdy delay (falling) due to ocp or ovp 0.3 s
ncp81245 www. onsemi.com 11 table 4. electrical characteristics unless otherwise stated: ?40 c < t a < 100 c; 4.75 v < v cc < 5.25 v ; c vcc = 0.1 f parameter unit max typ min test conditions pwm outputs output high voltage sourcing 500 a v cc ? 0.2 v output mid voltage no load 1.9 2.0 2.1 v output low voltage sinking 500 a 0.3 v rise and fall time cl (pcb) = 50 pf, vo =10% to 90% of vcc 5 ns tri?state output leakage gx = 2.0 v, x = 1?2, en = low ?1 1 a phase detection cspx phase disable voltage 4.75 v product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions.
ncp81245 www. onsemi.com 12 single phase electrical table follows table 5. electrical characteristics unless otherwise stated: ?40 c ncp81245 www. onsemi.com 13 general the ncp81245 is a three rail 3+3+1 phase pwm controller with a single serial intel proprietary interface control interface. serial vid for intel proprietary interface communication details please contact intel ? , inc. ncp81245 configurations the ncp81245 has four configuration pins that are secondary?functions on pwm pins. on power up a 10 a current is sourced from these pins through a resistor connected to this pin and the resulting voltage is measured. the following features will be programmed: ? intel proprietary interface address ? for intel proprietary interface address selection please see table below. ? for more information regrading intel proprietary interface addresses please contact intel, inc. ? phase doubler ? the multi?phase a rail can use a phase doubler from on semiconductor. ? options to enable doubling on the a rail is provided in the vboot configuration table ? switching frequency ? both multi?phase rails? per?phase switching frequency will be the same programmable value. ? the 1?phase fsw is programmed independently ? the fsw values are shown in the rosc table ? vboot ? addresses 00h, 01h, and 03 por vboot is 0v. ? address 02h por vboot is 1.05v ? vboot options are shown in the vboot table boot voltage vboot for the ncp81245 is externally programmed using a single resistor. see vboot pin voltages and the corresponding vboot level in the table below. during startup, the pin voltage is measured. this value cannot be changed after the initial power up sequence is complete. table 6. vboot pin 20 configuration resistor 3ph_a vboot 3ph_b vboot 1ph vboot rail a doubler 6.19 k 0 v 0 v 0 v no 14.7 k 0 v 0 v 0 v yes 24.9 k 0 v 0 v 1.05 v no 37.4 k 0 v 0 v 1.05 v yes 53.6 k 0 v 0 v 0.95 v no 73.2 k 0 v 0 v 0.95 v yes 97.6 k 0 v 0 v 0.8 v no 130 k 0 v 0 v 0.8 v yes 169 k 1.05 v 1.05 v 1.05 v no 215 k 1.05 v 1.05 v 1.05 v yes
ncp81245 www. onsemi.com 14 table 7. intel proprietary interface address pin 19 configuration pull?down resistor slew rate mv/ s 3ph_a address 3ph_b address 1ph address pin 24 tsense/ psys a max phases b max phases ncp81245 (3+3+1, pin 21 = pwm3_3ph_b, pin 26 = csp3_3ph_b) 4.3 k 30 00h 01h 02h psys 3 3 12.1 k 00h 01h 03h tsense 3 3 19.6 k 01h 00h 02h psys 3 3 31.6 k 01h 00h 03h tsense 3 3 49.9 k 10 00h 01h 02h psys 3 3 78.7 k 00h 01h 03h tsense 3 3 121 k 01h 00h 02h psys 3 3 174 k 01h 00h 03h tsense 3 3 psys the psys pin is an analog input to the ncp81245. it is a system input power monitor that facilitates the monitoring of the total platform system power. for more information regarding psys please contact intel, inc. remote sense amplifier (multiphase) a high performance high input impedance true differential amplifier is provided to accurately sense the output voltage of the regulator. the vsp and vsn inputs should be connected to the regulator?s output voltage sense points. the remote sense amplifier takes the difference of the output voltage with the dac voltage and adds the droop voltage to v difout v vsp v vsn 1.3 v v dac (eq. 1) v droop v csref this signal then goes through a standard error compensation network and into the inverting input of the error amplifier. the non?inverting input of the error amplifier is connected to the same 1.3 v reference used for the differential sense amplifier output bias. high performance voltage error amplifier (multiphase) a high performance error amplifier is provided for high bandwidth transient performance. a standard type iii compensation circuit is normally used to compensate the system. differential current feedback amplifiers (multiphase) each phase has a low offset dif ferential amplifier to sense that phase current for current balance. the inputs to the cspx pins are high impedance inputs. it is also recommended that the voltage sense element be no less than 0.5 m for accurate current balance. fine tuning of this time constant is generally not required. the individual phase current is summed into the pwm comparator feedback this way current is balanced via a current mode control approach. ccsn rcsn dcr lphase 1 2 swnx vout cspx csnx figure 5. dcr c l r csn phase csn ? = total current sense amplifier (multiphase) the ncp81245 uses a patented approach to sum the phase currents into a single temperature compensated total current signal. this signal is then used to generate the output voltage droop, total current limit, and the output current monitoring functions. the total current signal is floating with respect to csref. the current signal is the difference between cscomp and csref. the ref(n) resistors sum the signals from the output side of the inductors to create a low impedance virtual ground. the amplifier actively filters and gains up the voltage applied across the inductors to recover the voltage drop across the inductor series resistance (dcr). rth is placed near an inductor to sense the temperature of the inductor. this allows the filter time constant and gain to be a function of the rth ntc resistor and compensate for the change in the dcr with temperature.
ncp81245 www. onsemi.com 15 figure 6. the dc gain equation for the current sensing: v cscomp?csref rcs2 rcs1*rth rcs1 rth rph * iout total * dcr (eq. 2) set the gain by adjusting the value of the rph resistors. the dc gain should be set to the output voltage droop. if the voltage from cscomp to csref is less than 100 mv at iccmax then it is recommend increasing the gain of the cscomp amp. this is required to provide a good current signal to offset voltage ratio for the ilimit pin. when no droop is needed, the gain of the amplifier should be set to provide ~100 mv across the current limit programming resistor at full load. the values of rcs1 and rcs2 are set based on the 220k ntc and the temperature effect of the inductor and should not need to be changed. the ntc should be placed near the closest inductor. the output voltage droop should be set with the droop filter divider. the pole frequency in the cscomp filter should be set equal to the zero from the output inductor. this allows the circuit to recover the inductor dcr voltage drop current signal. ccs1 and ccs2 are in parallel to allow for fine tuning of the time constant using commonly available values. it is best to fine tune this filter during transient testing. f z dcr@25 c 2*pi*l phase (eq. 3) programming the current limit (multiphase) the current limit thresholds are programmed with a resistor between the ilimit and cscomp pins. the ilimit pin mirrors the voltage at the csref pin and mirrors the sink current internally to iout (reduced by the iout current gain) and the current limit comparators. the 100% current limit trips if the ilimit sink current exceeds 10 a for 50 s. the 150% current limit trips with minimal delay if the ilimit sink current exceeds 15 a. set the value of the current limit resistor based on the cscomp?csref voltage as shown below. r limit rcs2 rcs1*rth rcs1 rth rph * iout limit * dcr 10 (eq. 4) or r limit v cscom?csref@ilimit 10 (eq. 5) programming dac feed?forward filter (multiphase) the dac feed?forward implementation is realized by having a filter on the vsn pin. programming rvsn sets the gain of the dac feed?forward and cvsn provides the time constant to cancel the time constant of the system per the following equations. cout is the total output capacitance and rout is the output impedance of the system. figure 7. rvsn cout * rout * 453.6 10 6 (eq. 6) cvsn rout * cout rvsn (eq. 7) programming droop (multiphase) the signals cscomp and csref are differentially summed with the output voltage feedback to add precision voltage droop to the output voltage. figure 8. droop dcr * rcs rph programming iout (multiphase) the iout pin sources a current in proportion to the ilimit sink current. the voltage on the iout pin is monitored by the internal a/d converter and should be scaled with an external resistor to ground such that a load equal to iccmax generates a 2 v signal on iout. a
ncp81245 www. onsemi.com 16 pull?up resistor from 5 v v cc can be used to offset the iout signal positive if needed. r iout 2v*r limit 10 * rcs2 rcs1*rth rcs1 rth rph * iout icc_max * dcr (eq. 8) programming icc_max (multiphase) a resistor to ground on the imax pin programs these registers at the time the part is enabled. 10 a is sourced from these pins to generate a voltage on the program resistor. the resistor value should be no less than 10k. icc_max 21k r*10 a * 256 a 2v (eq. 9) programming tsense a temperature sense inputs are provided. a precision current is sourced out the output of the tsense pin to generate a voltage on the temperature sense network. the voltage on the temperature sense input is sampled by the internal a/d converter. a 100k ntc similar to the vishay ert?j1vs104ja should be used. rcomp1 is mainly used for noise. see the specification table for the thermal sensing voltage thresholds and source current. rcomp2 8.2k rntc 100k cfilter 0.1uf agnd agnd rcomp1 0.0 tsense figure 9. precision oscillator a programmable precision oscillator is provided. the clock oscillator serves as the master clock to the ramp generator circuit. this oscillator is programmed by a resistor to ground on the rosc pin. the oscillator frequency range is between 300 khz/phase to 1.2 mhz/phase. the rosc pin provides approximately 2 v out and the source current is mirrored into the internal ramp oscillator. the oscillator frequency is approximately proportional to the current flowing in the rosc resistor. table 8. 3 phase / 1 phase fsw v rosc (pin21 / pin22) resistor per phase fsw mph_a per phase fsw mph_b per phase fsw 1ph 6.19 k 1.2 mhz 1.2 mhz 1.2 mhz 14.7 k 1.1 mhz 1.1 mhz 1.1 mhz 24.9 k 1.0 mhz 1.0 mhz 1.0 mhz 37.4 k 900 khz 900 khz 900 khz 53.6 k 800 khz 800 khz 800 khz 73.2 k 700 khz 700 khz 700 khz 97.6 k 600 khz 600 khz 600 khz 130 k 500 khz 500 khz 500 khz 169 k 400 khz 400 khz 400 khz 215 k 300 khz 300 khz 300 khz the oscillator generates triangle ramps that are 0.5~2.5 v in amplitude depending on the vrmp pin voltage to provide input voltage feed forward compensation. the ramps are equally spaced out of phase with respect to each other and the single phase rail is set half way between phases 1 and 2 of the multi phase rail for minimum input ripple current. for use with on semiconductor?s phase doubler, the ncp81245 offers the user the ability to multiply the frequency of multiphase rail a. on the ncp81245, the switching frequency is increased by a factor of 2 when the phase doubler configuration is used. programming the ramp feed?forward circuit the ramp generator circuit provides the ramp used by the pwm comparators. the ramp generator provides voltage feed?forward control by varying the ramp magnitude with respect to the vrmp pin voltage. the vrmp pin also has a 4 v uvlo function. the vrmp uvlo is only active after the controller is enabled. the vrmp pin is high impedance input when the controller is disabled. the pwm ramp time is changed according to the following, v ramppk pkpp 0.1 * v vrmp (eq. 10)
ncp81245 www. onsemi.com 17 vin comp ? il duty vramp_pp figure 10. pwm comparators the non?inverting input of the comparator for each phase is connected to the summed output of the error amplifier (comp) and each phase current (il*dcr*phase balance gain factor). the inverting input is connected to the oscillator ramp voltage with a 1.3 v offset. the operating input voltage range of the comparators is from 0 v to 3.0 v and the output of the comparator generates the pwm output. during steady state operation, the duty cycle is centered on the valley of the sawtooth ramp waveform. the steady state duty cycle is still calculated by approximately vout/vin. during a transient event, the controller will operate in a hysteretic mode with the duty cycles pull in for all phases as the error amp signal increases with respect to all the ramps. phase detection sequence the ncp81245 normally operates as a 3?ph vcc_rail1 + 3?ph vcc_rail2 + 1?ph vcc_rail3. phases of the multi?phase rails can be disabled by pulling up csp pins to vcc. for example, to configure one of the 3 phase rails of the ncp81245 as a 1 phase rail, csp2 and csp3 of that rail must be pulled up to vcc on startup. both the single?phase rails and multi?phase rail b can be disabled by pulling all of their associated csp pins to vcc. phase 1 of multi?phase rail a cannot be disabled. the pwm outputs are logic?level devices intended for driving fast response external gate drivers or drmos. as each phase is monitored independently, operation approaching 100% duty cycle is possible. in addition, more than one pwm output can be on at the same time to allow overlapping phases.
ncp81245 www. onsemi.com 18 protection features under voltage lockouts there are several under voltage monitors in the system. hysteresis is incorporated within the comparators. ncp81245 monitors the 5 v v cc supply. the gate driver monitors both the gate driver v cc and the bst voltage. when the voltage on the gate driver is insufficient it will pull dron low and prevents the controller from being enabled. the gate driver will hold dron low for a minimum period of time to allow the controller to hold off its startup sequence. in this case the pwm is set to the mid state to begin soft start. dac gate driver pulls dron low during driver uvlo and calibration if dron is pulled low the controller will hold off its startup figure 11. gate driver uvlo restart soft?start soft start is implemented internally. a digital counter steps the dac up from zero to the target voltage based on the predetermined rate in the spec table. the pwm signals will start out open with a test current to collect data on phase count and for setting internal registers. after the configuration data is collected, if the controller is enabled the pwms will be set to 2.0 v mid state to indicate that the drivers should be in diode mode. dron will then be asserted. as the dac ramps the pwm outputs will begin to fire. each phase will move out of the mid state when the first pwm pulse is produced. when the controller is disabled the pwm signal will return to the mid state. figure 12.
ncp81245 www. onsemi.com 19 over current latch? off protection (multiphase) the ncp81245 compares a programmable current?limit set point to the voltage from the output of the current?summing amplifier. the level of current limit is set with the resistor from the ilim pin to cscomp. the current through the external resistor connected between ilim and cscomp is then compared to the internal current limit current i cl . if the current generated through this resistor into the ilim pin (ilim) exceeds the internal current?limit threshold current (i cl ) , an internal latch?off counter starts, and the controller shuts down if the fault is not removed after 50 s(shut down immediately for 150% load current) after which the outputs will remain disabled until the v cc voltage or en is toggled. the voltage swing of cscomp cannot go below ground. this limits the voltage drop across the dcr through the current balance circuitry. an inherent per?phase current limit protects individual phases if one or more phases stop functioning because of a faulty component. the over?current limit is programmed by a resistor on the ilim pin. the resistor value can be calculated by the following equations, equation related to the ncp81245 multiphase rails: r ilim i lim * dcr * rcs rph i cl (eq. 11) where i cl = 10 a r ph r cs rlim ilim cscomp cssum r ph r ph csref figure 13. under voltage monitor the output voltage is monitored at the output of the differential amplifier for uvlo. if the output falls more than 300 mv below the dac?droop voltage the uvlo comparator will trip sending the vr_rdy signal low. the 300 mv limit can be reprogrammed using the vr_ready_low limit register. over voltage protection the output voltage is also monitored at the output of the differential amplifier for ovp. during normal operation, if the output voltage exceeds the dac voltage by 400 mv, the vr_rdy flag goes low, and the output voltage will be ramped down to 0 v. the part will stay in this mode until the v cc voltage or en is toggled figure 14.
ncp81245 www. onsemi.com 20 ovp during normal operation mode during start up, the ovp threshold is set to 2.0 v. this allows the controller to start up without false triggering the ovp. figure 15. ovp behavior at startup single?phase rail the architecture of the single?phase rail makes use of a digitally enhanced, high performance, current mode rpm control method that provides excellent transient response while minimizing transient aliasing. the average operating frequency is digitally stabilized to remove frequency drift under all continuous mode operating conditions. at light load the single?phase rail automatically transitions into dcm operation to save power. single?phase rail remote sense error amplifier a high performance, high input impedance, true differential transconductance amplifier is provided to accurately sense the regulator output voltage and provide high bandwidth transient performance. the vsp and vsn inputs should be connected to the regulator?s output voltage sense points through filter networks described in the following droop section and the dac feedforward filter section. the remote sense error amplifier outputs a current proportional to the difference between the output voltage and the dac voltage: i comp gm v dac v vsp v vsn
(eq. 12) this current is applied to a standard t ype ii compensation network. single?phase rail voltage compensation the remote sense amplifier outputs a current that is applied to a type ii compensation network formed by external tuning components clf, rz and chf. vsp comp vsn clf rz chf vsn vsp dac gm figure 16. single?phase rail ? differential current feedback amplifier the single?phase controller has a low offset, differential amplifier to sense output inductor current. an external lowpass filter can be used to superimpose a reconstruction of the ac inductor current onto the dc current signal sensed across the inductor. the lowpass filter time constant should match the inductor l/dcr time constant by setting the filter pole frequency equal to the zero of the output inductor. this makes the filter ac output mimic the product of ac inductor current and dcr, with the same gain as the filter dc output. it is best to perform fine tuning of the filter pole during transient testing. f z dcr@25 c 2* *l (eq. 13)
ncp81245 www. onsemi.com 21 f p 1 2* * r phsp * rth r cssp r phsp rth r cssp *c cssp (eq. 14) forming the lowpass filter with an ntc thermistor (rth) placed near the output inductor, compensates both the dc gain and the filter time constant for the inductor dcr change with temperature. the values of r phsp and r cssp are set based on the ef fect of temperature on both the thermistor and inductor. the csp and csn pins are high impedance inputs, but it is recommended that the lowpass filter resistance not exceed 10 k in order to avoid of fset due to leakage current. it is also recommended that the voltage sense element (inductor dcr) be no less than 0.5 m for suf ficient current accuracy. recommended values for the external filter components are: c cssp l phase r phsp * rth r cssp r phsp rth r cssp * dcr (eq. 15) r phsp = 7.68 k r cssp = 14.3 k rth = 100 k , beta = 4300 using 2 parallel capacitors in the lowpass filter allows fine tuning of the pole frequency using commonly available capacitor values. the dc gain equation for the current sense amplifier output is: v curr rth r cssp r phsp rth r cssp * iout * dcr (eq. 16) csp csn rphsp rcssp t rth ccssp inductor to current sense amp pwm generator curr _ + av=1 comp figure 17. the amplifier output signal is combined with the comp and ramp signals at the pwm comparator inputs to produce the ramp pulse modulation (rpm) pwm signal. single?phase rail ? loadline programming (droop) an output loadline is a power supply characteristic wherein the regulated (dc) output voltage decreases by a voltage v droop , proportional to load current. this characteristic can reduce the output capacitance required to maintain output voltage within limits during load transients faster than those to which the regulation loop can respond. in the ncp81245, a loadline is produced by adding a signal proportional to output load current (v droop ) to the output voltage feedback signal ? thereby satisfying the voltage regulator at an output voltage reduced proportional to load current. v droop is developed across a resistance between the vsp pin and the output voltage sense point.
ncp81245 www. onsemi.com 22 vsp csp csn rphsp rcssp t rth ccssp to rdrpsp cdrpsp csnssp to vcc_sense current sense amp vsn vsp _ + av=1 gm figure 18. v droop r drpsp gm rth r cssp r phsp rth r cssp i out dcr the loadline is programmed by choosing r drpsp such that the ratio of voltage produced across r drpsp to output current is equal to the desired loadline. r drpsp loadline gm dcr r phsp rth r cssp rth r cssp (eq. 17) single?phase rail ? programming the dac feed?forward filter the dac feed?forward implementation for the single?phase rail is the same as for the multi?phase rails. the ncp81245 outputs a pulse of current from the vsn pin upon each increment of the internal dac following a dvid up command. a parallel rc network inserted into the path from vsn to the output voltage return sense point, vss_sense, causes these current pulses to temporarily decrease the voltage between vsp and vsn. this causes the output voltage during dvid to be regulated slightly higher, in order to compensate for the response of the droop function to the inductor current flowing into the charging output capacitors. rffsp sets the gain of the dac feed?forward and cffsp provides the time constant to cancel the time constant of the system per the following equations. cout is the total output capacitance of the system. vsp vsn rffsp cffsp csnssp to vss_sense dac dac forward vsn vsp dac feed? dac feedforward current from svid interface gm figure 19. r ffsp loadline * cout 1.35 nf (eq. 18) c ffsp 200 ns r ffsp (eq. 19) single?phase rail ? programming the current limit the current limit threshold is programmed with a resistor (r ilimsp ) from the ilim pin to ground. the current limit latches the single?phase rail off immediately if the ilim pin voltage exceeds the ilim threshold. set the value of the current limit resistor based on the equation shown below. a capacitor can be placed in parallel with the programming resistor to slightly delay activation of the latch if some tolerance of short overcurrent events is desired.
ncp81245 www. onsemi.com 23 csp csn ilim rphsp rcssp t rth ccssp inductor to rilimsp programming comparators overcurrent overcurrent current sense amp ocp ocp ref _ + av=1 gm figure 20. r ilimsp 1.3 v gm rth r cssp r phsp rth r cssp iout limit dcr when selecting the current limit it is necessary to take into account the additional inductor current due to the slew rate of the output voltage across the output capacitance during vid changes, as this excess current may cause the ocp limit to be exceeded. this excess current is given by: i cout dvout dt (eq. 20) where dvout dt is the maximum slew rate single?phase rail ? programming iout the iout pin sources a current in proportion to the ilimit sink current. the voltage on the iout pin is monitored by the internal a/d converter and should be scaled with an external resistor to ground such that a load equal to iccmax generates a 2 v signal on iout. a pull?up resistor from 5 v v cc can be used to offset the iout signal positive if needed. csp csn iout rphsp rcssp t rth ccssp inductor to rioutsp monitor current current sense amp iout _ + av=1 gm figure 21. r ioutsp 2v gm rth r cssp r phsp rth r cssp iccmax dcr single?phase rail pwm comparators the non?inverting input of each comparator (one for each phase) is connected to the summation of the output of the error amplifier (comp) and each phase current (i l *dcr*phase current gain factor). the inverting input is connected to the triangle ramp voltage of that phase. the output of the comparator generates the pwm output. a pwm pulse starts when the error amp signal (comp voltage) rises above the trigger threshold plus gained?up inductor current, and stops when the artificial ramp plus gained?up inductor current crosses the comp voltage. both edges of the pwm signals are modulated. during a transient event, the duty cycle can increase rapidly as the comp voltage increases with respect to the ramps, to provide a highly linear and proportional response to the step load. programming icc_max (single phase) a resistor to ground on the imax pin programs these registers at the time the part is enabled. 10 a is sourced from these pins to generate a voltage on the program resistor. the resistor value should be no less than 10k. icc_max 21h r max * 10 a * 256 a 4*2v (eq. 21)
ncp81245 www. onsemi.com 24 package dimensions qfn52 6x6, 0.4p case 485be issue b seating note 4 k 0.10 c (a3) a a1 d2 b 1 14 27 52 e2 52x l bottom view detail c top view side view d a b e 0.10 c pin one location 0.10 c 0.08 c c 40 e a 0.07 b c 0.05 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimensions: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30mm from terminal tip 4. coplanarity applies to the exposed pad as well as the terminals. dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.15 0.25 d 6.00 bsc d2 4.60 4.80 e 6.00 bsc 4.80 e2 4.60 e 0.40 bsc l 0.25 0.45 l1 0.00 0.15 note 3 plane dimensions: millimeters 0.25 4.80 0.40 4.80 52x 0.63 52x 6.40 6.40 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* detail b l1 detail a l alternate terminal constructions l 0.30 ref pitch 52x pkg outline l2 0.15 ref l2 detail c 8 places l2 detail a detail d 8 places 0.11 0.49 detail d on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does o n semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including ?typic als? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distrib utors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ncp81245/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative intel is a registered trademark of intel corporation in the u.s. and/or other countries. ?

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